The business of producing dynamic random access memory (DRAM) devices is a very competitive, high-volume business. Process efficiency and manufacturability, as well as product quality, reliability, and performance are the key factors that determine the economic success of such a venture.
Each cell within a DRAM device, an individually-addressable location for storing a single bit of digital data, is comprised of two main components: a field-effect access transistor and a capacitor. Each new generation of DRAM devices generally has an integration level that is four times that of the generation which it replaced. Such a quadrupling of device number per chip is always accompanied by a decrease in device geometries, and often by a decrease in operating voltages. As device geometries and operating voltages are decreased, the DRAM designer is faced with the difficult task of maintaining cell capacitance at an acceptable level. This must be accomplished without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process. All DRAM memories of 4-megabit and greater density utilize cell designs having three-dimensional capacitors. Although both trench and stacked capacitor designs have proven serviceable at the 4-megabit level, most manufacturers now seem to favor the stacked capacitor design for its manufacturability and somewhat higher yield.
In order to increase the capacitance of a DRAM memory cell capacitor, it has been determined to be advantageous to form a rough surface on the storage-node capacitor plates. One of the most successful techniques for creating a rough surface is the growth of hemispherical-grain (HSG) polycrystalline silicon (polysilicon) nodules or asperities on the surface on the surfaces of the storage-node plates. Although HSG polysilicon can be deposited via chemical vapor deposition, a selective-growth process using vacuum anneal is simpler and, thus, preferred. In order to prevent the shorting together of all the storage-node plates in the memory array, the growth of the HSG polysilicon asperities must be selective. In addition, experiments have shown that when a silicon dioxide layer is present at the edge of a storage node plate, deposition of a silicon nitride dielectric layer on the storage-node plate will be thinner near that edge, and will result in a current leakage path unless the thickness of the dielectric layer is increased, resulting in decreased capacitance for the same unit area. Thus it is preferable to deposit a silicon nitride dielectric layer on a silicon surface when an existing silicon nitride film is present at the edges of the surface. What is needed is a process flow for fabricating DRAM capacitors that addresses these issues.